An algebraic approach to compiler design by Sampaio A.

By Sampaio A.

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An-i an-i-1 ... ai ai-1 0 1 1 0 ... a0 1 0 1 s rn-1 ... ri ... ri-1 r0 ÙÖ ¾º¾½ ´n iµ-Cyclic left shifter a[n-1:0] cls(n, 20 ) b[0] r0 cls(n, 21 ) b[1] ... cls(n, 2m-1 ) b[m-1] r ÙÖ ¾º¾¾ Circuit of an n-cyclic left shifter CLS´nµ b[m-1:0] a[n-1:0] CLS(n) 1 inc(m) m r[n-1:0] ÙÖ ¾º¾¿ Circuit of an n-cyclic right shifter CRS´nµ ¿¾ an-1 ai ... ai-1 0 0 ... Ë Ø ÓÒ ¾º a0 A RITHMETIC C IRCUITS 0 1 0 1 0 1 0 1 s rn-1 ri ... ri-1 ... 22. 23. 24. Let n 2m be a power of two. An n-logic right shifter is a circuit with inputs a n 1 : 0 , select inputs b m 1 : 0 and outputs r n 1 : 0 satisfying r lrs´a b µ In analogy to the cyclic left shifter, the n-logic right shifter can be built by 2m 1 .

Of an n-3/2-adder. b[m-1] a b[j] b[0] a a ... 0m-1 0m-1-j 0 j 0m-1 m-operand addition tree s t 0 add(n+m) p[n+m-1:0] ÙÖ ¾º¾ ¾º º¿ ÅÙÐØ ÔÐ Circuit of an ´n mµ-multiplier Ø ÓÒ ÖÖ Ý× An addition tree with m operands is a circuit which takes as inputs m binary numbers and which outputs a carry save representation of their sum. 27. First, one generates binary representations of the m partial products St 1 . These are fed into an addition tree with m operands. The output of the tree is a carry save representation of the desired product.

The cost and the delay are ¾¼ Chdec ´1µ 0 Chdec ´nµ Chdec ´n 1µ · 2n Dhdec ´1µ 0 Dhdec ´nµ Dhdec ´n 1µ · max Dand Dor 1 ¡ ´Cand · Cor µ n=1 n>1 Ë Ø ÓÒ ¾º¿ x[n-2 : 0] BASIC C IRCUITS 0 x[0] hdec(n-1) U[L] 2n-1 x[n-1] Y[1] Y[0] 2n-1 2n-1 Y[H] ÙÖ ¾º Y[L] Recursive definition of an n-half decoder circuit In the induction step of the correctness proof the last x n 2 : 0 bits of U are set to one by induction hypothesis. If xn 1 0, then x n 2 : 0 x If xn 1 n 1 yH 02 yL U and 1, then x 2n yH U yL 1 1 · x n 2 : 0 and 2n 1 Thus, in both cases the last x bits of y are one.

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