Advanced ASIC Chip Synthesis: Using Synopsys® Design by Himanshu Bhatnagar

By Himanshu Bhatnagar

Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® describes the complex ideas and methods used for ASIC chip synthesis, formal verification and static timing research, utilizing the Synopsys suite of instruments. furthermore, the complete ASIC layout move method specified for VDSM (Very-Deep-Sub-Micron) applied sciences is roofed intimately.
The emphasis of this booklet is on real-time program of Synopsys instruments used to strive against quite a few difficulties noticeable at VDSM geometries. Readers could be uncovered to an efficient layout technique for dealing with advanced, sub-micron ASIC designs. value is put on HDL coding types, synthesis and optimization, dynamic simulation, formal verification, DFT experiment insertion, hyperlinks to structure, and static timing research. At each one step, difficulties concerning every one section of the layout circulate are pointed out, with ideas and work-arounds defined intimately. moreover, an important matters on the topic of format, including clock tree synthesis and back-end integration (links to structure) also are mentioned at size. moreover, the ebook comprises in-depth discussions at the fundamentals of Synopsys expertise libraries and HDL coding kinds, distinct in the direction of optimum synthesis ideas.
Advanced ASIC Chip Synthesis: utilizing Synopsys® DesignCompiler® and PrimeTime® is meant for an individual who's serious about the ASIC layout method, ranging from RTL synthesis to ultimate tape-out. objective audiences for this ebook are training ASIC layout engineers and graduate scholars project complicated classes in ASIC chip layout and DFT suggestions.
From the Foreword:
`This publication, written through Himanshu Bhatnagar, offers a accomplished review of the ASIC layout stream particular for VDSM applied sciences utilizing the Synopsis suite of instruments. It emphasizes the sensible matters confronted by means of the semiconductor layout engineer by way of synthesis and the combination of front-end and back-end instruments. conventional layout methodologies are challenged and detailed options are provided to assist outline the following new release of ASIC layout flows. the writer presents a variety of functional examples derived from real-world events that would end up helpful to practising ASIC layout engineers in addition to to scholars of complicated VLSI classes in ASIC design'.
Dr Dwight W. Decker, Chairman and CEO, Conexant structures, Inc., (Formerly, Rockwell Semiconductor Systems), Newport seashore, CA, USA.

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Extra resources for Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime®

Sample text

A number of EDA tool vendors have developed the formal verification tools. However, only recently, Synopsys also introduced to the market its own formal verification tool called Formality. The main difference between formal methods and dynamic simulation is that the former technique verifies the design by proving that the structure and functionality of two designs are logically equivalent. Dynamic simulation methods can only probe certain paths of the design that are sensitized, thus may not catch a problem present elsewhere.

This technique ASIC DESIGN METHODOLOGY 9 is important since the scan-flops generally have different delays associated with them as compared to their non-scan equivalent flops (or normal flops). ITAG or boundary scan is primarily used for testing the board connections, without unplugging the chip from the board. The ITAG controller and surrounding logic may also be generated directly by DC. A number of steps must be performed in order to perform successful synthesis. These will be discussed later in subsequent chapters.

It is assumed that the functionality of the design has been verified by dynamically simulating it at the RTL level. , map the design to the gates belonging to the specified technology library. setup file for DC. setup file for PT. The first file is the setup file for DC and is used for synthesis, while the second file is associated with PT and defines the required setup to be used for static timing analysis . setup file search_path =search_path + {..... setup file set searchpath [list. 3 Pre-Layout Steps The following sub-sections illustrate the steps involved during the pre-layout phase.

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