A Pipelined Multi-core MIPS Machine Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

This monograph relies at the 3rd author's lectures on computing device structure, given in the summertime semester 2013 at Saarland college, Germany. It incorporates a gate point development of a multi-core laptop with pipelined MIPS processor cores and a sequentially constant shared memory.

The e-book comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and in addition of a cache established sequentially constant shared reminiscence. This opens the best way to the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and therefore deterministic. against this the reference versions opposed to which correctness is proven are nondeterministic. the improvement of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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R ∈ Bn . 5 Drivers and Main Memory 55 yin yin α OC y y α β β Fig. 27. Open collector driver and its timing diagram collector drivers, and main memory. 5 that a design that works in the digital model also works in the detailed hardware model. For tristate drivers and main memory this will not be the case. 1 Open Collector Drivers and Active Low Signal A single open collector driver y and its detailed timing is shown in Fig. 27. If the input yin is 0, then the open collector driver also outputs 0.

Working out the proof sketch from [10], we formalize timing analysis and show by induction on depth that, with proper timing analysis, the detailed model is simulated by the digital model. This justifies the use of the digital model as long as we use only gates and registers. In the very simple Sect. R of hardware configurations h. As we aim at the construction of memory systems, we extend in Sect. 5 both circuit models with open collector drivers, tristate drivers, buses, and a model of main memory.

Moreover, expression e is pure. Proof. Let b ∈ B and let xi be a variable. We define the literal xbi = b=1 b=0. 17, xbi = 1 ↔ xi = b . (2) Let a = a[1 : n] ∈ Bn and let x = x[1 : n] be a vector of variables. We define the monomial n xai i . 18) ↔ ∀i ∈ [1 : n] : xi = ai (2) ↔x=a. Thus, we have m(a) = 1 ↔ x = a . 6 (3) The term switching function comes from electrical engineering and stands for a Boolean function. 6 Boolean Algebra 27 We define the support S(f ) of f as the set of arguments a, where f takes the value f (a) = 1: S(f ) = {a | a ∈ Bn ∧ f (a)} .

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